So far EEPROM (electrically erasable and programmable ROM) has been used as one of the non-volatile semiconductor storage device.
FIG. 5 illustrates the reading of conventional EEPROM. The memory cell 116 consists of one selection transistor 117 and one storage transistor 118 which are connected to each other in serial. The drain of the selection transistor 117 is connected to the bit line BL, the source is formed commonly with the drain of the storage transistor 118 and the gate is connected to the word line WL. The storage transistor 118 has the floating gate and control gate, the control gate is connected to the control line CL and the source is connected to the common source line SS. The control line is connected to the sense line SL via the transistor 124.
The storage transistor 118 stores information when the floating gate is electrified (at writing or erasing). The electric charge is poured into and extracted from the floating gate by the F-N (Fowler-Nordheim) current via a partial thin film (tunnel oxide film) between the floating gate and drain.
When the floating gate is electrified negatively, the threshold voltage (Vth) of the storage transistor increases. This state is referred to as the erasing state (the state "1"). On the other hand, the floating gate is electrified positively, the threshold voltage (Vth) of the storage transistor decreases. This state is referred to as the writing state (the state "0").
At reading, the intermediate voltage (Vref) between the threshold voltage of the erasing state and that of the writing state is supplied to the sense line SL. If the word line WL is selected, the voltage of the sense line SL is impressed to the control line CL. If the state of the floating gate is "0", a channel is formed between the source and the drain of the storage transistor 118 and then the storage transistor 118 becomes conductive. On the other hand, the state of the floating gate is "1", a channel is not formed between the source and the drain of the storage transistor 118 and, therefore, the storage transistor 118 becomes nonconductive.
If the word line WL is selected, a specified current flows into the memory cell 116 according to the information stored in the storage transistor 118 because the selection transistor 117 has become conductive. The current is supplied to the memory cell 116 by the pull-up PMOS 126 via the bit line selection transistor 128 and the data line DL. The voltage of the data line DL, which depends on the specified current into the memory cell 116 and the current supplied by the pull-up PMOS 126, is amplified and output by the sense amplifier (S. A.) 114.
FIG. 6 is an electric characteristics diagram which illustrates an operation of the sense amplifier 114. A stable voltage point of the data line DL is the intersections (d1 and d2) of the current curves of the memory cells (the state "0" and the state "1") and that of the pull-up PMOS 126. A judgment voltage of the sense amplifier 114 is set at or around the center between the intersection (d1) when the state of the memory cell is "0" and the other intersection (d2) when the state of the memory cell is "1". A data is judged as "0" if the voltage of the data line DL is lower than the judgment voltage and it is judged as "1" if such voltage of the data line DL is higher.